Semiconductor device

ABSTRACT

A semiconductor device includes: a semiconductor layer, a first semiconductor region provided on a major surface of the semiconductor layer, a second semiconductor region provided in a surface portion of the first semiconductor region, a trench extending through the second semiconductor region and the first semiconductor region to the semiconductor layer, a first insulating film provided on an inner wall of the trench, a third semiconductor region filling the trench below an interface between the semiconductor layer and the first semiconductor region, a second insulating film provided on the third semiconductor region, a gate electrode filling the trench above the second insulating film. A portion of the first insulating film in contact with the semiconductor layer is opened. The semiconductor layer is in contact with the third semiconductor region through the opened portion.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2005-361962, filed on Dec. 15,2005 and the prior Japanese Patent Application No. 2006-281316, filed onOct. 16, 2006; the entire contents of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a semiconductor device, and more particularlyto a semiconductor device having a trench gate structure.

2. Background Art

Trench gate type MOSFETs (Metal Oxide Semiconductor Field EffectTransistors) are known as semiconductor devices suitable to powerelectronics and other applications requiring high withstand voltage andlow ON resistance (see, e.g., JP 2002-083963A).

JP 2002-083963A discloses a MOSFET having a trench that is formed toreach an N-type substrate through a P-type well layer and an N-typedrift layer. An N-type source layer is formed in the surface of the welllayer. A buried electrode of polysilicon is formed via an insulatingfilm in a region extending from the drift layer to the substrate in thetrench. A gate electrode of polysilicon is formed via an insulating filmin a region extending from the source layer through the well layer tothe drift layer in the trench. The buried electrode is electricallyinsulated from the gate electrode.

In the configuration disclosed in JP 2002-083963A, the buried electrodeis completely covered with the insulating film and does not form a p-njunction with the drift layer. Therefore, when the dopant concentrationin the drift layer is increased for reducing ON resistance, it isdifficult to completely deplete the drift layer and to obtain highwithstand voltage.

SUMMARY OF THE INVENTION

According to an aspect of the invention, there is provided asemiconductor device including: a semiconductor layer of a firstconductivity type; a first semiconductor region of a second conductivitytype provided on a major surface of the semiconductor layer; a secondsemiconductor region of the first conductivity type provided in asurface portion of the first semiconductor region; a trench extendingthrough the second semiconductor region and the first semiconductorregion to the semiconductor layer; a first insulating film provided onan inner wall of the trench; a third semiconductor region of the secondconductivity type filling the trench below an interface between thesemiconductor layer and the first semiconductor region; a secondinsulating film provided on the third semiconductor region; a gateelectrode filling the trench above the second insulating film; a firstmain electrode connected to the second semiconductor region; and asecond main electrode provided on a side opposite to the major surfaceof the semiconductor layer, wherein a portion of the first insulatingfilm in contact with the semiconductor layer is opened, and thesemiconductor layer is in contact with the third semiconductor regionthrough the opened portion.

According to other aspect of the invention, there is provided asemiconductor device including: a semiconductor layer of a firstconductivity type; a first semiconductor region of a second conductivitytype provided on a major surface of the semiconductor layer; a secondsemiconductor region of the first conductivity type provided in asurface portion of the first semiconductor region; a trench extendingthrough the second semiconductor region and the first semiconductorregion to the semiconductor layer; a first insulating film provided onan inner wall of the trench, a portion of the first insulating film incontact with the semiconductor layer having an opening; a thirdsemiconductor region of the second conductivity type filling the trenchbelow an interface between the semiconductor layer and the firstsemiconductor region and being in contact with the semiconductor layerthrough the opening formed in the portion of the first insulating film;a second insulating film provided on the third semiconductor region; agate electrode filling the trench above the second insulating film; afirst main electrode connected to the second semiconductor region; asecond main electrode provided on a side opposite to the major surfaceof the semiconductor layer; a plurality of terminal semiconductorregions of the second conductivity type filling terminal trenches andjuxtaposed with the semiconductor layer being interposed therebetween,the terminal trenches being formed in the semiconductor layer in aterminal section outside a device section in which the gate electrode,the first semiconductor region, and the second semiconductor region areformed; and an interlayer insulating film provided adjacent to anoutermost semiconductor region of the plurality of terminalsemiconductor regions and buried on the major surface side of thesemiconductor layer.

According to other aspect of the invention, there is provided asemiconductor device including: a semiconductor layer of a firstconductivity type; a first semiconductor region of a second conductivitytype provided on a major surface of the semiconductor layer; a secondsemiconductor region of the first conductivity type provided in asurface portion of the first semiconductor region; a trench extendingthrough the second semiconductor region and the first semiconductorregion to the semiconductor layer; a gate insulating film provided on aninner wall of the trench; a gate electrode filling the trench via thegate insulating film; a first main electrode connected to the secondsemiconductor region; a second main electrode provided on a sideopposite to the major surface of the semiconductor layer; a plurality ofterminal semiconductor regions of the second conductivity type fillingterminal trenches and juxtaposed with the semiconductor layer beinginterposed therebetween, the terminal trenches being formed in thesemiconductor layer in a terminal section outside a device section inwhich the gate electrode, the first semiconductor region, and the secondsemiconductor region are formed; and an interlayer insulating filmprovided adjacent to an outermost semiconductor region of the pluralityof terminal semiconductor regions and buried on the major surface sideof the semiconductor layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic view illustrating the cross-sectional structure ofthe main part of a semiconductor device according to a first embodimentof the invention.

FIG. 2 is a schematic view illustrating the planar structure of the mainpart of the semiconductor device according to the first embodiment.

FIG. 3 is a cross-sectional view taken along line A1-A1 in FIG. 2.

FIG. 4 is a cross-sectional view taken along line A2-A2 in FIG. 2.

FIGS. 5 to 12 are process cross-sectional views illustrating the mainpart of a process of manufacturing a semiconductor device according tothe first embodiment.

FIG. 13 is a schematic view illustrating the cross-sectional structureof the main part of a semiconductor device according to a thirdembodiment of the invention.

FIG. 14 is a schematic view illustrating the cross-sectional structureof the main part of a semiconductor device according to a fourthembodiment of the invention.

FIGS. 15 to 18 are process cross-sectional views illustrating the mainpart of a process of manufacturing a semiconductor device according tothe fourth embodiment.

FIG. 19 is a schematic view illustrating the cross-sectional structureof the main part of a semiconductor device according to a fifthembodiment of the invention.

FIG. 20 is a schematic view illustrating the planar pattern of the mainconfiguration in a semiconductor device according to a sixth embodimentof the invention.

FIG. 21 is a cross-sectional view taken along line D-D in FIG. 20.

FIG. 22 is a cross-sectional view taken along line E-E in FIG. 20.

FIG. 23 is a cross-sectional view taken along line F-F in FIG. 20.

FIG. 24 is a schematic view illustrating the planar pattern of the mainconfiguration in a semiconductor device according to a seventhembodiment of the invention.

FIG. 25 is a cross-sectional view taken along line G-G in FIG. 24.

FIG. 26 is a process cross-sectional view illustrating the main part ofa process of manufacturing a semiconductor device according to theseventh embodiment.

FIG. 27 is a schematic view illustrating the cross-sectional structureof the main part of a semiconductor device according to an eighthembodiment of the invention.

FIG. 28 is a schematic view illustrating the planar pattern of the mainconfiguration in a semiconductor device according to a ninth embodimentof the invention.

FIG. 29 is a schematic view illustrating the cross-sectional structureof the main part of a semiconductor device according to a tenthembodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the invention will now be described with reference to thedrawings.

FIRST EMBODIMENT

FIG. 1 is a schematic view illustrating the cross-sectional structure ofthe main part of a semiconductor device 1 according to a firstembodiment of the invention.

FIG. 2 is a schematic view illustrating the planar structure of the mainpart of the semiconductor device 1.

FIG. 3 is a cross-sectional view taken along line A1-A1 in FIG. 2. FIG.1 shows a cross section taken along line B-B in FIG. 3.

FIG. 4 is a cross-sectional view taken along line A2-A2 in FIG. 2.

This embodiment is described assuming the first conductivity type asP-type and the second conductivity type as N-type.

On a major surface of a P⁺⁺-type silicon substrate 2, a semiconductorlayer (drift layer or drain layer) 4 of P-type silicon and a firstsemiconductor region (base region) 6 of N⁻-type silicon are successivelyprovided. A p-n junction is formed between the semiconductor layer 4 andthe first semiconductor region 6.

Trenches T are provided to extend through the first semiconductor region6 to the semiconductor layer 4. The trench T extends in the directiongoing through the page in FIG. 1 and is provided generally perpendicularto the major surface of the substrate 2. The bottom of the trench T doesnot reach the substrate 2. An insulating film 8, 16 is formed on thesidewall of the trench T.

Below the interface between the semiconductor layer 4 and the firstsemiconductor region 6, the trench T is filled with a thirdsemiconductor region 13 of N-type monocrystalline silicon or N-typepolysilicon (polycrystalline silicon). The third semiconductor region 13has a dopant concentration of 10 ¹⁸/cm³ or less, for example. Part ofthe insulating film 8 in contact with the semiconductor layer 4 has anopening through which the semiconductor layer 4 is in contact with thethird semiconductor region 13. The dopant concentration in the thirdsemiconductor region 13 being set to 10 ¹⁸/cm³ or less is preferable incompletely depleting the third semiconductor region 13.

In this embodiment, the insulating film 8 is not provided at the bottomof the trench T where there is an opening. Therefore the N-type thirdsemiconductor region 13 forms a p-n junction with the P-typesemiconductor layer 4 at the bottom of the trench T. The bottom of thetrench T is formed in a planar configuration, and hence the p-n junctioninterface between the third semiconductor region 13 and thesemiconductor layer 4 also has a planar configuration. The insulatingfilm 8 is interposed between the side face of the third semiconductorregion 13 and the semiconductor layer 4. The area of the thirdsemiconductor region 13 covered with the insulating film 8 is largerthan the area of the third semiconductor region 13 being in contact withthe semiconductor layer 4. To provide an opening in the insulating film8 at the bottom of the trench T, the bottom of the trench T may beentirely opened as shown in FIG. 1, or part of the bottom may be opened.For example, the insulating film 8 may be extended to the bottom of thetrench T, and only the vicinity of the center of the bottom may be leftopen.

An insulating film 15 is provided above the third semiconductor region13, and the trench T is filled with a gate electrode 18 above theinsulating film 15. The upper end of the insulating film 15 is locatedslightly below the interface between the semiconductor layer 4 and thefirst semiconductor region 6. The gate electrode 18 is electricallyinsulated from the third semiconductor region 13 by the insulating film15. An insulating film 16 is interposed between the gate electrode 18and the first semiconductor region 6. The gate electrode 18 is made ofP⁺-type polysilicon, for example, but is not limited thereto. Othersemiconductors and metals can also be used.

In the surface portion of the first semiconductor region 6 is provided asecond semiconductor region 7 of P⁺-type silicon. The interface betweenthe first semiconductor region 6 and the second semiconductor region 7is located slightly below the upper end of the gate electrode 18. Theinsulating film 16 is interposed between the gate electrode 18 and thesecond semiconductor region 7.

The second semiconductor region 7 is connected to a first main electrode(source electrode) 21. The first main electrode 21 is electricallyinsulated from the gate electrode 18 by an interlayer insulating film25. A second main electrode (drain electrode) 22 is provided on thesurface opposite to the major surface of the substrate 2.

As shown in FIG. 3, the gate electrode 18 and the third semiconductorregion 13 have extraction portions 18 b and 13 b, respectively,extracted in the same direction. An insulating film 33 is interposedbetween the extraction portion 18 b of the gate electrode 18 and theextraction portion 13 b of the third semiconductor region 13. Aninsulating film 34 is interposed between the extraction portion 13 b ofthe third semiconductor region 13 and the first semiconductor region 6.

The extraction portion 18 b of the gate electrode 18 is connected to agate extraction interconnect 27 through a connection hole h1 formed inthe interlayer insulating film 25. The extraction portion 13 b of thethird semiconductor region 13 is connected to the first main electrode21 through a connection hole h2 passing through the extraction portion18 b of the gate electrode 18 and the interlayer insulating film 25. Theinterlayer insulating film 25 is interposed between the first mainelectrode 21 filling the connection hole h2 and the extraction portion18 b of the gate electrode 18 to electrically insulate the first mainelectrode 21 from the gate electrode 18.

In the semiconductor device 1 configured as above, when a prescribedbias voltage is applied to the gate electrode 18, a channel is formed inthe first semiconductor region 6 opposed to the gate electrode 18 viathe insulating film 16. Thus the path between the first main electrode21 and the second main electrode 22 is turned on.

The semiconductor device 1 of this embodiment has a so-called superjunction structure on the bottom side of the trenches T where P-typeregions and N-type regions are repeatedly juxtaposed and form p-njunctions through the bottom of the trenches T. Depletion of thesemiconductor layer 4 and the third semiconductor region 13 can befacilitated through the bottom of the trench T serving as a p-njunction. Therefore, even when the dopant concentration in thesemiconductor layer 4 serving as a drift layer for passing current isincreased for reducing ON resistance, the semiconductor layer 4 and thethird semiconductor region 13 can be completely depleted, and thedecrease of withstand voltage during application of drain-source voltagecan be prevented. That is, a semiconductor device 1 having highwithstand voltage and low ON resistance is provided.

The insulating film 8 interposed between the side face of the thirdsemiconductor region 13 and the semiconductor layer 4 can prevent dopantin one of the third semiconductor region 13 and the semiconductor layer4 from diffusing into the other. Thus it is possible to prevent thevariation of dopant concentration in the current path and the resultingincrease of ON resistance.

Because the p-n junction at the bottom of the trench T is a junction ofmaterials of the same kind (silicon), leak current is less likely tooccur.

For example, the semiconductor device of this embodiment is configuredso that the dopant concentration in the semiconductor layer 4 is2.8×10¹⁷/cm³, the pitch of the trenches T is 0.5 micrometer, the widthof the trench T along the arranged direction is 0.3 micrometer, thedepth of the portion of the trench T filled with the third semiconductorregion 13 is 1 micrometer, and the length from the upper end of thethird semiconductor region 13 to the upper end of the secondsemiconductor region 7 is 1.2 micrometers. A withstand voltage of 36 Vwas achieved for this semiconductor device. However, the withstandvoltage was only 7 V in the configuration where the insulating film isformed also at the bottom of the trench T and there is no junctionbetween the semiconductor layer 4 and the third semiconductor region 13.

In the present embodiment, as shown in FIG. 2 and FIG. 4 that shows theA2-A2 cross section in FIG. 2, an N⁺-type back gate region 65 isprovided so as to divide the source region 7. The back gate region 65 isconnected to the source electrode 21. This can facilitate releasingcarriers through the back gate region 65 to the source electrode 21 andprevent device destruction.

Note that the configuration of the back gate region 65 is not limited todividing the source region 7. It is sufficient if a carrier releasingpath from the base region 6 to the source electrode 21 can beestablished. Thus the back gate region 65 can be provided in any way ifthe base region 6 is electrically connected to the source electrode 21through the back gate region 65.

Next, an example method for manufacturing a semiconductor device 1 isdescribed.

FIGS. 5 to 12 are process cross-sectional views illustrating the mainpart of a process of manufacturing a semiconductor device 1.

As shown in FIG. 5, on a P⁺⁺-type silicon substrate 2 having a highdopant concentration, a semiconductor layer 4 of P-type silicon and afirst semiconductor region 6 of N⁻-type silicon are successively formed.

Next, as shown in FIG. 6, an oxide film 141 selectively formed on thesurface of the first semiconductor region 6 is used as a mask to formtrenches T extending through the first semiconductor region 6 to thesemiconductor layer 4 by anisotropic etching such as RIE (Reactive IonEtching). The bottom of the trench T does not reach the substrate 2.

Next, as shown in FIG. 7, an insulating film 8 is formed on the innerwall (sidewall and bottom face) of the trench T. The insulating film 8is a silicon oxide film formed by thermal oxidation, for example.

Next, as shown in FIG. 8, the insulating film 8 exclusively at thebottom 11 of the trench T is removed by anisotropic etching such as RIE.Thus the semiconductor layer 4 is exposed inside the trench T throughthe bottom 11 of the trench T where the insulating film 8 is removed.

At this time, the bottom 11 of the trench T can be etched to have aplanar configuration. Then the p-n junction to be formed between a thirdsemiconductor region 13 filling the bottom side of the trench T and thesemiconductor layer 4 has a planar interface, which facilitates completedepletion.

Next, the trench T is completely buried with N-type polysilicon by CVD(Chemical Vapor Deposition) using a silicon source gas and an N-typedopant source gas, for example. Then the polysilicon is etched back to aposition below the interface between the semiconductor layer 4 and thefirst semiconductor region 6.

Thus, as shown in FIG. 9, a third semiconductor region 13 of N-typepolysilicon filling the trench T is formed below the interface betweenthe semiconductor layer 4 and the first semiconductor region 6.

Note that the third semiconductor region 13 may be formed by anothermethod. Specifically, after the trench T is buried with polysilicon,N-type dopant is implanted into the polysilicon. Then the implantedN-type dopant is diffused by heat treatment to form N-type polysilicon,which is etched back to a position below the interface between thesemiconductor layer 4 and the first semiconductor region 6, therebycompleting the third semiconductor region 13. Even for a fine trench T(i.e., with a large aspect ratio), the trench T can be easily buriedwith polysilicon.

When the third semiconductor region 13 is formed, dopant diffusionbetween the third semiconductor region 13 and the semiconductor layer 4is prevented because the insulating film 8 has already been providedbetween the side face of the third semiconductor region 13 and thesemiconductor layer 4. Thus it is possible to prevent the variation ofdopant concentration in the current path and the resulting increase ofON resistance. Furthermore, it is easy to desirably control the dopantconcentration in the third semiconductor region 13 even if the trenchesT have a fine pitch.

Next, as shown in FIG. 10, etching is used to remove the insulating film8 formed on the sidewall of the portion of the trench T above the thirdsemiconductor region 13, that is, the portion that is not filled withthe third semiconductor region 13.

Next, as shown in FIG. 11, an insulating film 15 is formed on the thirdsemiconductor region 13, and an insulating film 16 is formed on thesidewall of the trench T above the third semiconductor region 13. Theinsulating films 15, 16 are silicon oxide films formed by thermaloxidation, for example.

Next, after the trench T above the insulating film 15 is buried withpolysilicon, P-type dopant is implanted into the polysilicon. Then theimplanted P-type dopant is diffused by heat treatment to form P⁺-typepolysilicon, which is etched back to a position below the opening at theupper end of the trench T.

Thus, as shown in FIG. 12, a gate electrode 18 of P⁺-type polysilicon isformed, which faces the first semiconductor region 6 across theinsulating film 16. Note that the gate electrode 18 may be of N-type, orsemiconductor other than silicon. Furthermore, the gate electrode 18 isnot limited to semiconductor, but may be made of metal.

Next, an interlayer insulating film 25 is formed. The interlayerinsulating film 25 fills the trench T above the gate electrode 18 asshown in FIG. 1 and overlies the extraction portion 18 b of the gateelectrode 18 as shown in FIG. 3. The interlayer insulating film 25 is asilicon oxide film, for example.

Next, the surface of the first semiconductor region 6 around the trenchT is subjected to ion implantation and thermal diffusion of P-typedopant. Thus a second semiconductor region 7 of P⁺-type silicon isformed in the surface portion of the first semiconductor region 6 aroundthe trench T.

Next, a first main electrode 21 of aluminum is formed on the secondsemiconductor region 7 and the interlayer insulating film 25 bysputtering, for example. Thus the first main electrode 21 iselectrically connected to the second semiconductor region 7.Furthermore, as shown in FIG. 3, the first main electrode 21 iselectrically connected to the third semiconductor region 13 through aconnection hole formed in the interlayer insulating film 25.

The gate electrode 18 is electrically connected to the gate extractioninterconnect 27 through a connection hole formed in the interlayerinsulating film 25 as shown in FIG. 3. A second main electrode 22 isformed on the backside of the substrate 2. Thus a semiconductor device 1shown in FIGS. 1 to 4 is obtained.

In the following, other embodiments of the invention are described.Elements similar to those described earlier are marked with the samereference numerals and not described in detail.

SECOND EMBODIMENT

The second embodiment is different from the first embodiment in themethod of forming the third semiconductor region 13.

In this embodiment again, like the first embodiment, no insulating filmis formed at the bottom of the trench T. The semiconductor layer 4exposed inside the trench T through the bottom of the trench T is usedas a base crystal to epitaxially grow N-type silicon. The growth isterminated before reaching the interface between the semiconductor layer4 and the first semiconductor region 6. Thus a third semiconductorregion 13 is formed, which fills the trench T below the interfacebetween the semiconductor layer 4 and the first semiconductor region 6and forms a junction with the semiconductor layer 4 at the bottom of thetrench T.

The epitaxial growth of the third semiconductor region 13 is selectiveepitaxial growth exclusively onto the semiconductor layer 4 exposedthrough the bottom of the trench T. Therefore the crystal face (crystalorientation) is aligned, the crystallinity of the third semiconductorregion 13 can be improved, and leak current can be reduced. Inparticular, this embodiment is effective in obtaining the thirdsemiconductor region 13 as a large crystal.

THIRD EMBODIMENT

FIG. 13 is a schematic view illustrating the cross-sectional structureof the main part of a semiconductor device 31 according to a thirdembodiment of the invention.

In this embodiment, the conductivity type of each element is reversedwith respect to the first embodiment. More specifically, assuming thefirst conductivity type as N-type and the second conductivity type asP-type, the device comprises a substrate 102 of N⁺⁺-type silicon, asemiconductor layer (drift layer) 104 of N-type silicon, a firstsemiconductor region (base region) 106 of P⁻-type silicon, a secondsemiconductor region (source region) 107 of N⁺-type silicon, a thirdsemiconductor region 113 of P-type silicon or polysilicon, and a gateelectrode 118 of N⁺-type silicon.

In this embodiment again, depletion of the semiconductor layer 104 andthe third semiconductor region 113 can be facilitated through the bottomof the trench T serving as a p-n junction. Therefore, even when thedopant concentration in the semiconductor layer 104 is increased forreducing ON resistance, the semiconductor layer 104 and the thirdsemiconductor region 113 can be completely depleted, and the decrease ofwithstand voltage during application of drain-source voltage can beprevented.

FOURTH EMBODIMENT

FIG. 14 is a schematic view illustrating the cross-sectional structureof the main part of a semiconductor device 41 according to a fourthembodiment of the invention.

In this embodiment again, like the first embodiment, the trench T belowthe interface between the semiconductor layer 4 and the firstsemiconductor region 6 is filled with a third semiconductor region 13 ofN-type silicon or N-type polysilicon. A portion of the insulating filmin contact with the semiconductor layer 4 is opened, and thesemiconductor layer 4 is in contact with the third semiconductor region13 through the opened portion.

In this embodiment, the insulating film on the side face of the trench Thas an opening, and the N-type third semiconductor region 13 forms a p-njunction with the P-type semiconductor layer 4 at the side face of thetrench T. From the viewpoint of preventing dopant diffusion between thethird semiconductor region 13 and the semiconductor layer 4, the area ofthe p-n junction therebetween is preferably smaller than the area of theportion of the third semiconductor region 13 covered with insulatingfilms 8 a, 8 b.

In this embodiment again, depletion of the semiconductor layer 4 and thethird semiconductor region 13 can be facilitated through the p-njunction at the side face of the trench T. Therefore, even when thedopant concentration in the semiconductor layer 4 is increased forreducing ON resistance, the semiconductor layer 4 and the thirdsemiconductor region 13 can be completely depleted, and the decrease ofwithstand voltage during application of drain-source voltage can beprevented.

Next, an example method for manufacturing a semiconductor device 41 isdescribed.

FIGS. 15 to 18 are process cross-sectional views illustrating the mainpart of a process of manufacturing a semiconductor device 41.

A trench T is formed to extend through the first semiconductor region 6to the semiconductor layer 4, and an insulating film 8 a is formed onthe inner wall (sidewall and bottom face) of the trench T. These stepsare conducted similarly to the first embodiment.

Then, as shown in FIG. 15, the insulating film 8 a is etched so as toleave only the bottom and a portion slightly above the bottom of thetrench T.

Next, N-type silicon is laterally grown from the side face of the trenchT that is not covered with the insulating film 8 a. Thus, as shown inFIG. 16, a third semiconductor region 13 is formed, which fills thebottom side of the trench T so as to completely cover the insulatingfilm 8 a.

Next, as shown in FIG. 17, an insulating film 5 is formed on the thirdsemiconductor region 13, and an insulating film 8 b is formed on thesidewall of the trench T above the third semiconductor region 13.

Next, as shown in FIG. 18, the insulating film 5 on the thirdsemiconductor region 13 is removed by anisotropy etching. Then the thirdsemiconductor region 13 is epitaxially grown to a position slightlybelow the interface between the semiconductor layer 4 and the firstsemiconductor region 6 as shown in FIG. 14. Subsequently, like the firstembodiment, the steps described above are continued from FIG. 11.

FIFTH EMBODIMENT

FIG. 19 is a schematic view illustrating the cross-sectional structureof the main part of a semiconductor device 51 according to a fifthembodiment of the invention.

In this embodiment, a second semiconductor region 57 is selectivelyprovided around the periphery of the trench T in the surface of thefirst semiconductor region 6. Between the trenches T in the surface ofthe first semiconductor region 6, the second semiconductor regions 57are not linked laterally with each other.

SIXTH EMBODIMENT

FIG. 20 is a schematic view illustrating the planar pattern of the mainconfiguration in a semiconductor device according to a sixth embodimentof the invention.

FIG. 21 is a cross-sectional view taken along line D-D in FIG. 20.

FIG. 22 is a cross-sectional view taken along line E-E in FIG. 20.

FIG. 23 is a cross-sectional view taken along line F-F in FIG. 20.

The cross section taken along line C-C in FIG. 20 has the samecross-sectional structure as that shown in FIG. 1 described above.

In this embodiment, a contact portion for connecting the thirdsemiconductor region 13 to the source electrode (first main electrode)21 is provided halfway along the extending direction (X direction inFIGS. 20 and 22) of the trench T. For example, after the step of FIG. 8described above, the trench T is buried with polysilicon, and thepolysilicon is etched back to a position below the interface between thedrift layer 4 and the base region 6. At this time, a portion of thepolysilicon is not etched back to the position below the interfacebetween the drift layer 4 and the base region 6, but is left behind inthe trench T.

More specifically, a portion of the third semiconductor region 13 fillsthe trench T from the bottom of the trench T up to the source region 7.The surface portion 13 a of the third semiconductor region 13 fillingthe trench T has a higher dopant concentration (N⁺-type) than the otherportion of the third semiconductor region 13, and is in contact with thesource electrode 21 provided on the source region 7. The thirdsemiconductor region 13 is connected to the source electrode 21 throughthe surface portion 13 a having a high dopant concentration (N⁺-type).Thus the contact resistance between the third semiconductor region 13and the source electrode 21 can be reduced.

The third semiconductor region 13 is connected to the source electrode21. Furthermore, an N⁺-type back gate region 66 is provided in a portionneighboring the surface portion 13 a of the third semiconductor region13 via the oxide film 8 so as to divide the source region 7. The backgate region 66 is also connected to the source electrode 21. This canfacilitate releasing carriers to the source electrode 21 upon avalanchebreakdown and prevent device destruction.

Note that the configuration of the back gate region 66 is not limited todividing the source region 7. It is sufficient if a carrier releasingpath from the base region 6 to the source electrode 21 can beestablished. Thus the back gate region 66 can be provided in any way ifthe base region 6 is electrically connected to the source electrode 21through the back gate region 66.

In this embodiment, the third semiconductor region 13 is in contact withthe source electrode 21 directly above the trench T in the devicesection where a main current path is formed. This configuration canshorten the carrier ejection path as compared with the configurationwhere the third semiconductor region 13 is extracted outside the devicesection and connected to the source electrode 21 as shown in FIG. 3described above. Accordingly, upon avalanche breakdown, the carrierejection efficiency can be enhanced, which is effective for preventingdevice destruction.

Because the portion of the third semiconductor region 13 filling thetrench from the bottom to the top is provided halfway along theextending direction (X direction) of the trench T, the gate electrode 18is divided in the X direction as shown in FIGS. 20 and 22. Thus, in thisembodiment, gate interconnects 30 a, 30 b are provided for each group ofgate electrodes 18 divided by the third semiconductor region 13. Eachgate electrode 18 is divided by the third semiconductor region 13 intotwo portions, one of which is in cross contact with and connected to thegate interconnect 30 a. The other portion is in cross contact with andconnected to the gate interconnect 30 b. The gate interconnect 30 a andthe gate interconnect 30 b are connected to a gate pad (not shown), andthereby the gate electrodes 18 are electrically connected to each other.

Note that the portion of the third semiconductor region 13 filling thetrench T from the bottom to the top and connected to the sourceelectrode 21 may be repeated at a plurality of locations. In this caseagain, gate interconnects can be provided for each group of gateelectrodes divided by the third semiconductor region 13.

SEVENTH EMBODIMENT

FIG. 24 is a schematic view illustrating the planar pattern of the mainconfiguration in a semiconductor device according to a seventhembodiment of the invention.

FIG. 25 is a cross-sectional view taken along line G-G in FIG. 24.

In the semiconductor device according to this embodiment, theconfiguration of the device section (cell) including the gate electrode18, the base region 6, the source region 7, and the third semiconductorregion 13 is the same as that in the embodiments described above.According to this configuration of the device section, as describedabove, a p-n junction between the drift layer 4 and the thirdsemiconductor region 13 is formed at the bottom of the trench T.Depletion can be facilitated through this p-n junction. Therefore, evenwhen the dopant concentration in the drift layer 4 is increased (to adopant concentration of about 10¹⁷/cm³, for example) for reducing ONresistance, a desired withstand voltage can be ensured. However, it ismore difficult to maintain withstand voltage in the terminal sectionthan in the device section. Therefore, when there is such a highly-dopedlayer in the terminal section, it is difficult to maintain withstandvoltage in the terminal section.

Thus, in this embodiment, a plurality of (e.g., two in this embodiment)terminal trenches T1, T2 are formed in the drift layer 4 in the terminalsection outside the device section. The terminal trenches T1, T2 arefilled with semiconductor having a conductivity type opposite to that ofthe drift layer 4 to form terminal semiconductor regions 13 b, 13 c.Furthermore, an interlayer insulating film 40 buried on the majorsurface side of the drift layer 4 is provided adjacent to the outermostsemiconductor region 13 c of the terminal semiconductor regions 13 b, 13c.

The terminal trenches T1, T2 and the insulating film 8 formed on theinner surface of the sidewall thereof are formed in the same process andat the same time as the trench T and the insulating film 8 in the devicesection, and results in the state shown in FIG. 8. Then the trenches T,T1, T2 are buried with N-type polysilicon, for example. In the trench Tof the device section, the buried polysilicon is etched back to aposition below the interface between the drift layer 4 and the baseregion 6. However, the polysilicon in the terminal trenches T1, T2 isnot etched back to the position below the interface between the driftlayer 4 and the base region 6, but is left behind in the trenches T1,T2.

The surface portion 13 a of the terminal semiconductor region 13 b, 13 chas a higher dopant concentration (N⁺-type) than the other portion ofthe terminal semiconductor region 13 b, 13 c, and is in contact with thesource electrode provided on the source region 7. The surface portion ofthe drift layer 4 interposed between the terminal trenches T1 and T2 isalso provided with a contact region 35 having a high dopantconcentration (N⁺-type), which is also in contact with the sourceelectrode.

Like the device section, no insulating film is formed at the bottom ofthe terminal trench T1, T2. The drift layer 4 forms a p-n junction withthe terminal semiconductor region 13 b, 13 c. Between the terminaltrenches T1 and T2 (terminal semiconductor regions 13 b and 13 c), nobase region 6 is formed, but a drift layer 4 is interposed. That is, theN-type terminal semiconductor regions 13 b, 13 c and the P-type driftlayer 4 are alternately juxtaposed via insulating films 8. Therefore,when a voltage is applied between the drain and the source, a depletionlayer can be extended in the juxtaposed portion of the terminalsemiconductor regions 13 b, 13 c and the drift layer 4. Thus asufficient withstand voltage can be ensured in the terminal.

FIG. 26 is a schematic view illustrating a method for forming aninterlayer insulating film 40 buried on the major surface side of thedrift layer 4 and adjacent to the outermost semiconductor region 13 c.

After the terminal trenches T1, T2 and the terminal semiconductorregions 13 b, 13 c filling them are formed, an etching mask 80 is formedon the terminal trenches T1, T2 (terminal semiconductor regions 13 b, 13c) as shown in FIG. 26A. The etching mask 80 is used as a mask to etchthe drift layer 4 outside the outermost semiconductor region 13 c by CDE(Chemical Dry Etching). As a result of this etching, a trench t isformed on the frontside of the drift layer 4 as shown in FIG. 26B. Thenthe trench t is buried with an interlayer insulating film (e.g., siliconoxide film) 40. The distance between the drain potential portion and thesource potential portion can be increased by the amount corresponding tothe depth of the interlayer insulating film 40. Thus the electric fieldconcentration on the terminal surface portion is alleviated, and thewithstand voltage is enhanced.

In this embodiment, the trench t to be buried with the interlayerinsulating film 40 is formed by CDE. Therefore the drift layer 4 can beetched isotropically. Thus, even if the edge of the etching mask 80 isnot accurately aligned with the boundary between the drift layer 4 andthe insulating film 8 provided on the side face on the terminal side ofthe outermost semiconductor region 13 c, the drift layer 4 outside theinsulating film 8 can be completely removed.

The number of terminal trenches T1, T2 and terminal semiconductorregions 13 b, 13 c filling them is not limited to two, but may be threeor more.

EIGHTH EMBODIMENT

FIG. 27 is a schematic view illustrating the cross-sectional structureof the main part of a semiconductor device according to an eighthembodiment of the invention.

In this embodiment, a trench t and an interlayer insulating film 40buried therein are formed in advance beside the outermost terminaltrench T2. Then the terminal trenches T1, T2 are buried with N-typepolysilicon, for example, to form N-type terminal semiconductor regions13 b, 13 c with a P-type drift layer 4 being interposed therebetween.The polysilicon in the terminal trenches T1, T2 is extracted above thesurface of the terminal section and connected to a source electrode (notshown).

In this embodiment again, when a voltage is applied between the drainand the source, a depletion layer can be extended in the juxtaposedportion of the terminal semiconductor regions 13 b, 13 c and the driftlayer 4. Furthermore, the distance between the drain potential portionand the source potential portion can be increased by the amountcorresponding to the depth of the interlayer insulating film 40. Thusthe electric field concentration on the terminal surface portion isalleviated, and the withstand voltage is enhanced.

NINTH EMBODIMENT

FIG. 28 is a schematic view illustrating the planar pattern of the mainconfiguration in a semiconductor device according to a ninth embodimentof the invention.

In the seventh and eighth embodiment described above, the inventorsfound that the electric field tends to concentrate on the terminalsection, particularly in the vicinity of the outermost semiconductorregion 13 c. From the viewpoint of alleviating the electric fieldconcentration in the vicinity of the outermost semiconductor region 13c, the dopant concentration in the terminal semiconductor region 13 b onthe device section side is preferably made higher than the dopantconcentration in the outermost semiconductor region 13 c. When thedopant concentration in the terminal semiconductor region 13 b on thedevice section side is made higher than the dopant concentration in theoutermost semiconductor region 13 c, the electric field concentrationpoint can be shifted from the outermost semiconductor region 13 c to theterminal semiconductor region 13 b on the device section side. Thus theelectric field concentration in the vicinity of the outermostsemiconductor region 13 c can be alleviated.

However, the amount of dopant in the semiconductor regions 13 b, 13 c isnot highly controllable. Hence, in this embodiment shown in FIG. 28, thepattern width is made larger in the terminal semiconductor region 13 bon the device section side than in the outermost semiconductor region 13c. Thus the dopant concentration in the terminal semiconductor region 13b on the device section side is made higher than the dopantconcentration in the outermost semiconductor region 13 c.

TENTH EMBODIMENT

FIG. 29 is a schematic view illustrating the cross-sectional structureof the main part of a semiconductor device according to a tenthembodiment of the invention.

Comparing with the seventh to ninth embodiment described above, thisembodiment is the same in the configuration of the terminal section, butdifferent in the configuration of the device section. More specifically,the trench T in the device section is formed shallower than the terminaltrenches T1, T2, and the third semiconductor region 13 forming a p-njunction with the drift layer 4 is not provided below the gate electrode18.

In this embodiment again, when a voltage is applied between the drainand the source, a depletion layer can be extended in the juxtaposedportion of the terminal semiconductor regions 13 b, 13 c and the driftlayer 4. Furthermore, the distance between the drain potential portionand the source potential portion can be increased by the amountcorresponding to the depth of the interlayer insulating film 40. Thusthe electric field concentration on the terminal surface portion isalleviated, and the withstand voltage is enhanced.

In FIG.29, the semiconductor device having a structure of trench-gatetype is exemplarily shown, however, the invention is not limited to thisspecific structure but includes semiconductor devices having a structureof planar-gate type. Further, the MOS gate transistor structure can bereplaced to p-n diode structure or Schottky diode structure. That is,the MOS gate structure of this embodiment may be replaced to variouskinds of device structures, and these variants are also included in theinvention.

Embodiments of the invention have been described with reference to theexamples. However, the invention is not limited thereto, but variousmodifications can be made within the spirit of the invention.

The semiconductor region may be formed in a floating structure, insteadof being connected to the first main electrode (source electrode).However, complete depletion of the semiconductor region and thesemiconductor layer (drift layer) is facilitated more effectively whenthe semiconductor region is connected to the first main electrode.

The semiconductor region and the gate electrode are not limited to beingextracted in the same direction as shown in FIG. 3, but may be extractedin opposite directions.

Besides silicon oxide film, the insulating film and the interlayerinsulating film may be made of silicon nitride film or the like. Eachsemiconductor element may be made of semiconductors other than silicon(e.g., Ge, SiGe, SiC, GaAs, GaN, etc.).

1. A semiconductor device comprising: a semiconductor layer of a firstconductivity type; a first semiconductor region of a second conductivitytype provided on a major surface of the semiconductor layer; a secondsemiconductor region of the first conductivity type provided in asurface portion of the first semiconductor region; a trench extendingthrough the second semiconductor region and the first semiconductorregion to the semiconductor layer; a first insulating film provided onan inner wall of the trench; a third semiconductor region of the secondconductivity type filling the trench below an interface between thesemiconductor layer and the first semiconductor region; a secondinsulating film provided on the third semiconductor region; a gateelectrode filling the trench above the second insulating film; a firstmain electrode connected to the second semiconductor region; and asecond main electrode provided on a side opposite to the major surfaceof the semiconductor layer, wherein a portion of the first insulatingfilm in contact with the semiconductor layer is opened, and thesemiconductor layer is in contact with the third semiconductor regionthrough the opened portion.
 2. The semiconductor device according toclaim 1, wherein the third semiconductor region is connected to thefirst main electrode.
 3. The semiconductor device according to claim 2,wherein a portion of the third semiconductor region fills the trenchfrom the bottom of the trench up to the second semiconductor region, andthe third semiconductor region has a surface portion in contact with thefirst main electrode.
 4. The semiconductor device according to claim 3,wherein the surface portion of the third semiconductor region has ahigher dopant concentration than the other portion of the thirdsemiconductor region.
 5. The semiconductor device according to claim 1,further comprising a back gate region connected to the first mainelectrode is selectively provided on the first semiconductor region, theback gate region having a higher dopant concentration than the firstsemiconductor region.
 6. The semiconductor device according to claim 1,wherein the opening of the first insulating film is provided at thebottom of the trench.
 7. A semiconductor device comprising: asemiconductor layer of a first conductivity type; a first semiconductorregion of a second conductivity type provided on a major surface of thesemiconductor layer; a second semiconductor region of the firstconductivity type provided in a surface portion of the firstsemiconductor region; a trench extending through the secondsemiconductor region and the first semiconductor region to thesemiconductor layer; a first insulating film provided on an inner wallof the trench, a portion of the first insulating film in contact withthe semiconductor layer having an opening; a third semiconductor regionof the second conductivity type filling the trench below an interfacebetween the semiconductor layer and the first semiconductor region andbeing in contact with the semiconductor layer through the opening formedin the portion of the first insulating film; a second insulating filmprovided on the third semiconductor region; a gate electrode filling thetrench above the second insulating film; a first main electrodeconnected to the second semiconductor region; a second main electrodeprovided on a side opposite to the major surface of the semiconductorlayer; a plurality of terminal semiconductor regions of the secondconductivity type filling terminal trenches and juxtaposed with thesemiconductor layer being interposed therebetween, the terminal trenchesbeing formed in the semiconductor layer in a terminal section outside adevice section in which the gate electrode, the first semiconductorregion, and the second semiconductor region are formed; and aninterlayer insulating film provided adjacent to an outermostsemiconductor region of the plurality of terminal semiconductor regionsand buried on the major surface side of the semiconductor layer.
 8. Thesemiconductor device according to claim 7, wherein the terminalsemiconductor region forms a junction with the semiconductor layer atthe bottom of the trench.
 9. The semiconductor device according to claim7, wherein the terminal semiconductor region is connected to the firstmain electrode.
 10. The semiconductor device according to claim 7,wherein the surface portion of the terminal semiconductor region is incontact with the first main electrode.
 11. The semiconductor deviceaccording to claim 10, wherein the surface portion of the terminalsemiconductor region has a higher dopant concentration than the otherportion of the terminal semiconductor region.
 12. The semiconductordevice according to claim 7, further comprising a contact regionconnected to the first main electrode is provided on the semiconductorlayer interposed between the terminal trenches.
 13. The semiconductordevice according to claim 7, wherein the dopant concentration in theoutermost semiconductor region is made lower than the dopantconcentration in the terminal semiconductor region on the device sectionside.
 14. A semiconductor device comprising: a semiconductor layer of afirst conductivity type; a first semiconductor region of a secondconductivity type provided on a major surface of the semiconductorlayer; a second semiconductor region of the first conductivity typeprovided in a surface portion of the first semiconductor region; atrench extending through the second semiconductor region and the firstsemiconductor region to the semiconductor layer; a gate insulating filmprovided on an inner wall of the trench; a gate electrode filling thetrench via the gate insulating film; a first main electrode connected tothe second semiconductor region; a second main electrode provided on aside opposite to the major surface of the semiconductor layer; aplurality of terminal semiconductor regions of the second conductivitytype filling terminal trenches and juxtaposed with the semiconductorlayer being interposed therebetween, the terminal trenches being formedin the semiconductor layer in a terminal section outside a devicesection in which the gate electrode, the first semiconductor region, andthe second semiconductor region are formed; and an interlayer insulatingfilm provided adjacent to an outermost semiconductor region of theplurality of terminal semiconductor regions and buried on the majorsurface side of the semiconductor layer.
 15. The semiconductor deviceaccording to claim 14, wherein the terminal semiconductor region forms ajunction with the semiconductor layer at the bottom of the trench. 16.The semiconductor device according to claim 14, wherein the terminalsemiconductor region is connected to the first main electrode.
 17. Thesemiconductor device according to claim 14, wherein the surface portionof the terminal semiconductor region is in contact with the first mainelectrode.
 18. The semiconductor device according to claim 17, whereinthe surface portion of the terminal semiconductor region has a higherdopant concentration than the other portion of the terminalsemiconductor region.
 19. The semiconductor device according to claim14, further comprising a contact region connected to the first mainelectrode is provided on the semiconductor layer interposed between theterminal trenches.
 20. The semiconductor device according to claim 14,wherein the dopant concentration in the outermost semiconductor regionis made lower than the dopant concentration in the terminalsemiconductor region on the device section side.